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Memory-stall clock cycles = Read-stall cycles + Write-stall cycles Write-stall cycles = ((Writes/program) x write miss rate x Write miss penalty) + Write buffer stalls
Two main effects on performance:
- The lower the CPI, the more pronounced the impact of stall cycles
- The main memory system is unlikely to improve as fast as processor cycle time. When calculating CPI, the cache miss penalty is measured in CPU clock cycles needed for a miss. Thus if the main memories of two machines have teh same absolute access time, a higher CPU clock rate leads to a larger miss penalty.
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